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1 lt1103/LT1105 offline switching regulator load regulation danger!! lethal voltages present C see text n 1% line and load regulation with no optocoupler n switch frequency up to 200khz n internal 2a switch and current sense (lt1103) n internal 1a totem-pole driver (LT1105) n start-up mode draws only 200 m a n fully protected against overloads n overvoltage lockout of main supply n protected against underdrive or overdrive to fet n operates in continuous or discontinuous mode n ideal for flyback and forward topologies n isolated flyback mode has fully floating outputs the lt ? 1103 offline switching regulator is designed for high input voltage applications using an external fet switch whose source is driven by the open collector output of the lt1103. the lt1103 is optimized for 15w to 100w applications. for higher power applications or additional switch current flexibility, the LT1105 is available and its totem pole output drives the gate of an external fet. unique design of the lt1103/LT1105 eliminates the need for an optocoupler while still providing 1% load and line regulation in a magnetic flux-sensed converter. this sig- nificantly simplifies the design of offline power supplies and reduces the number of components which must cross the isolation barrier to one, the transformer. the lt1103/LT1105 current mode switching techniques are well suited to transformer isolated flyback and forward topologies while providing ease of frequency compensa- tion with a minimum of external components. low exter- nal part count for a typical application combines with a fully isolated flyback 100khz 50w converter with load regulation compensation i out (a) 0 v out (v) 5.05 5.15 5.25 8 lt1103 ta02 4.95 4.85 4.75 2 4 6 10 4.80 4.90 5.00 5.10 5.20 1 3 579 220v ac 270v ac 85v ac 110v ac features descriptio n u n up to 250w isolated mains converter n up to 50w isolated telecom converter n fully isolated multiple outputs n distributed power conversion networks applicatio n s u typical applicatio n u 220k 1w 499 w 39 m f 35v 1000pf 100 w 1n4148 13k 1% 4.75k 1% buk426-800a mbr2045 10 m h 5v 10a 50v 470 m f *50v 3600 m f windings for optional 12v dc outputs 10 w 1 m f 25v 220 m f 385v bav21 bav21 390pf 1.5ke300a 5w mur150 bridge rectifier + line filter 85v ac to 270v ac + transformer data: coiltronics ctx110228-3 l (pri) = 1.6mh n pri :n sec = 1:0.05 n bias :n sec = 1:0.27 18.7k 0.047 m f 1n4148 330 w 0.1 m f lt1103 ta13 *output capacitor is three 1200 m f, 50v capacitors in parallel to achieve required ripple current rating and low esr. optional output filter 0.047 m f v c v sw gnd osc 15v lt1103 v in fb danger!! high voltage!! + + + + + , ltc and lt are registered trademarks of linear technology corporation.
2 lt1103/LT1105 200khz maximum switching frequency to achieve high power density. performance at switching frequencies above 100khz may be degraded due to internal timing constraints associated with fully isolated flyback mode. included are the oscillator, control, and protection cir- cuitry such as current limit and overvoltage lockout. switch frequency and maximum duty cycle are adjustable. bootstrap circuitry draws 200 m a for start-up of isolated topologies. a 5v reference as well as a 15v gate bias are available to power external primary-side circuitry. no external current sense resistor is necessary with lt1103 because it is integrated with the high current switch. the LT1105 brings out the input to the current limit amplifier and requires the use of an external sense resistor. the lt1103/LT1105 have unique features not found on other offline switching regulators. adaptive antisat switch drive allows wide ranging load currents while maintaining high efficiency. the external fet is protected from insuf- ficient or excessive gate drive voltage with a drive detec- tion circuit. an externally activated shutdown mode reduces total supply current to less than 200 m a, typical for standby operation. fully isolated and regulated outputs can be generated in the optional isolated flyback mode without the need for optocouplers or other isolated feed- back paths. dangerous and lethal potentials are present in offline circuits! before proceeding any further, the reader is warned that caution must be used in the construction, testing and use of offline circuits. high voltage, ac line-connected potentials are present in these circuits. extreme caution must be used in working with and making connections to these circuits. repeat: offline circuits contain dangerous, ac line-connected high voltage potentials. use caution. all testing performed on an offline circuit must be done with an isolation transformer connected between the offline circuit's input and the ac line. users and constructors of offline circuits must observe this precaution when connecting test equipment to the circuit to avoid electric shock. repeat: an isolation transformer must be connected between the circuit input and the ac line if any test equipment is to be connected. v in .......................................................................... 30v v sw output voltage (lt1103) ................................. 50v v sw output current (200ns)(LT1105) ................. 1.5a v c , fb, osc, ss ........................................................ 6v i lim (LT1105) ........................................................... 3v 0vlo input current ............................................... 1ma lead temperature (soldering, 10 sec.)................ 300 c maximum operating ambient temperature range lt1103c .............................................. 0 c to 70 c LT1105c .............................................. 0 c to 70 c maximum operating junction temperature range lt1103c ............................................. 0 c to 100 c LT1105c ............................................ 0 c to 100 c LT1105i ......................................... C 40 c to 125 c storage temperature range ................ C65 c to 150 c descriptio n u war i g! u u absolute m axi m u m ratings w ww u (note 1)
3 lt1103/LT1105 package/order i n for m atio n w u u order part number order part number t jmax = 100 c, q ja = 130 c/w 1 2 3 45 6 7 8 top view gnd 15v v sw i lim v in osc fb v c n8 package 8-lead pdip 15v v in osc gnd v c fb v sw t7 package 7-lead to-220 front view 7 6 5 4 3 2 1 case is connected to ground. leads are formed t jmax = 100 c, q ja = 50 c/w consult factory for military grade parts. t jmax = 100 c, q ja = 100 c/w 1 2 3 4 5 6 7 top view n package 14-lead pdip pins 1 and 7 must be tied together 14 13 12 11 10 9 8 pwrgnd ovlo fb v c 5v ss gnd v sw nc nc 15v v in osc i lim order part number lt1103ct7 symbol parameter conditions min typ max units i q supply current 8v < v in < 30v, after device has started l 10 20 30 ma i start start-up current v in < v in start threshold l 200 400 m a industrial grade l 450 m a v in start threshold l 14.5 16.0 17.5 v v in shutdown threshold note: switching stops when v sw < 10v (lt1103) l 5.0 7.0 8.0 v note: switching stops when v gate < 10v (LT1105) v ref 5v reference voltage l 4.80 4.95 5.20 v v ref line regulation 10v < v in < 30v l 0.025 0.1 %/ v v ref load regulation 0ma < i l < 20ma l 0.025 0.05 %/ma v ref short-circuit current commercial grade l 25 60 110 ma industrial grade l 20 120 ma 15v short-circuit current commercial grade l 30 130 ma industrial grade l 25 140 ma v gate 15v gate bias reference 17 < v in < 30v, 0ma < i l < 30ma l 13.8 15.0 16.2 v 15v dropout voltage v in = 15v, i l = 30ma l 2.0 2.5 v 15v short-circuit current l 30 70 130 ma sf oscillator scaling factor fb = 4v, v c = open, measured at v sw , i sw = 25ma, 36 40 44 hz ? m f ovlo = 5v, f osc = sf/c osc, 40khz < f osc < 200khz l 32 40 48 hz ? m f oscillator valley voltage 2.0 v oscillator peak voltage 4.5 v electrical characteristics LT1105cn LT1105in LT1105cn8 LT1105in8 v in = 20v, v c = 0.85v, ovlo = 0v, v sw open, t a = 25 c, unless otherwise noted.
4 lt1103/LT1105 v in = 20v, v c = 0.85v, ovlo = 0v, v sw open, t a = 25 c, unless otherwise noted. electrical characteristics symbol parameter conditons min typ max unit dc preset max switch duty cycle fb = 4v, v c = open, f osc = 40khz, i sw = 25ma, l 58 65 72 % (lt1103) note: maximum duty cycle can be altered at osc pin preset max switch duty cycle fb = 4v, v c = open, f osc = 40khz, i sw = 25ma, l 56 63 70 % (LT1105) note: maximum duty cycle can be altered at osc pin industrial grade l 55 75 % ovlo threshold overvoltage lockout threshold at which switching is inhibited l 2.3 2.5 2.7 v industrial grade l 2.2 2.8 v ovlo input bias current ovlo = 2v, measured out of pin (note 2) l 1.0 3.0 m a v fb fb threshold voltage i(v c ) = 0ma 4.425 4.50 4.575 v l 4.400 4.50 4.600 v fb input bias current fb = v fb (note 3) l 51020 m a industrial grade l 422 m a change in fb input fb = v fb , v c = 1v to 4v (note 3) 8 11 13 m a/v bias current with change in v c l 71114 m a/v industrial grade l 615 m a/v fb threshold line regulation 10v < v in < 30v l 0.025 0.10 %/v gm error amp transconductance d i(v c ) = 50 m a 9000 12000 17500 m mho l 6000 12000 20000 m mho industrial grade l 5000 24000 m mho a v error amp voltage gain 1v < v c < 3v l 500 1250 v/v industrial grade l 450 v/v v c switching threshold switch duty cycle = 0% l 0.85 1.25 1.4 v shutdown threshold voltage l 50 150 250 mv industrial grade l 50 300 mv error amp source current l 150 275 m a error amp sink current l 1.5 3 4.5 ma industrial grade l 0.7 4.5 ma error amp clamp voltage fb = 4.75v l 0.3 0.7 0.9 v fb = 4.0v l 4.2 4.4 4.6 v soft-start charging current ss = 0v l 25 40 60 m a industrial grade l 20 75 m a soft-start reset current v in = 6v, ss = 0.3v l 12 ma output switch leakage v sw = 45v l 500 m a (lt1103) v sw = 15v l 200 m a bv switch breakdown voltage i sw = 5ma l 50 70 v (lt1103) v sw current limit (lt1103) duty cycle = 25% (note 4) l 2.0 2.5 3.0 a output switch on resistance l 0.4 0.75 w (lt1103) d i in i q increase during switch on time i sw = 0.5a to 1.5a l 30 50 ma/a d i sw (lt1103) switch output high level i sw = 200ma, v gate = 15v l 13.00 13.5 v (LT1105) i sw = 750ma, v gate = 15v l 12.50 13.2 v switch output high level i sw = 200ma, v gate = 15v l 12.75 v industrial grade i sw = 750ma, v gate = 15v l 12.25 v
5 lt1103/LT1105 electrical characteristics symbol parameter conditons min typ max unit switch output low level i sw = 200ma l 0.25 0.50 v (LT1105) i sw = 750ma l 0.75 1.50 v rise time (LT1105) c l = 1000pf 50 ns fall time (LT1105) c l = 1000pf 20 ns i lim threshold voltage (LT1105) duty cycle = 25% (note 5) l 300 375 450 mv low switch drive lockout measured at v sw (lt1103) l 9.0 9.5 10.5 v threshold measured at 15v gate bias reference (LT1105) high switch drive lockout measured at v sw (lt1103) l 17.0 18.5 20.0 v threshold measured at 15v gate bias reference (LT1105) the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ovlo pin is clamped with a 5.5v zener and can sink a maximum input current of 1ma. note 3: fb input bias current changes as a function of the v c pin voltage. rate of change of fb input bias current is 11 m a/v of change on v c . by including a resistor in series with the fb pin, load regulation can be set to zero. note 4: current limit on v sw is constant for dc < 35% and decreases for dc > 35% due to internal slope compensation circuity. the lt1103 switch current limit is given by i lim = 1.76 (1.536 C dc) above 35% duty cycle. note 5: the current limit threshold voltage is constant for dc < 35% and decreases for dc > 35% due to internal slope compensation circuitry. the LT1105 switch current limit threshold voltage is given by v lim = 0.225 (1.7 C dc) above 35% duty cycle. input voltage (v) 0 0 supply current (ma) 5 10 15 20 25 5 10 15 20 lt1103 g01 25 30 i start i shut 25? typical perfor m a n ce characteristics u w start-up supply current vs input voltage quiescent supply current vs input voltage supply current vs input voltage input voltage (v) 0 12 quiescent supply current (ma) 13 15 16 17 22 19 10 20 25 lt1103 g03 14 20 21 18 515 30 35 40 125? 25? ?5? input voltage (v) 0 start-up supply current ( m a) 300 400 500 12 lt1103 g02 200 50 0 3 6 9 15 100 150 250 350 450 125 c 25 c ?5 c v in = 20v, v c = 0.85v, ovlo = 0v, v sw open, t a = 25 c, unless otherwise noted.
6 lt1103/LT1105 typical perfor m a n ce characteristics u w temperature ( c) ?5 14.5 v in start-up threshold (v) 15.0 15.5 16.0 16.5 17.0 17.5 ?5 25 75 125 lt1103 g07 175 ?0 0 50 100 150 v in start-up threshold vs temperature v in shutdown threshold vs temperature temperature (?) ?5 v in shutdown threshold (v) 7.4 7.7 8.0 125 lt1103 g08 7.1 6.8 6.5 ?5 25 75 175 ?0 0 50 100 150 output switch frequency vs temperature temperature (?) ?5 35 output switch frequency (khz) 37 41 43 45 ?5 25 50 150 lt1103 g09 39 ?0 0 75 100 125 c osc = 1000pf preset switch maximum duty cycle vs temperature switch oscillator frequency vs capacitance capacitance (pf) 100 10 switch frequency (khz) 100 1000 1000 10000 lt1103 g11 overvoltage lockout threshold vs temperature temperature (?) ?5 overvoltage lockout threshold (v) 2.6 2.8 3.0 125 lt1103 g12 2.4 2.2 2.0 ?5 25 75 175 150 100 50 0 ?0 temperature (?) ?5 preset switch duty cycle (%) 69 72 75 125 lt1103 g10 66 63 60 ?5 25 75 175 150 100 50 0 ?0 c osc = 1000pf quiescent supply current vs temperature shutdown supply current vs v c voltage shutdown supply current vs input voltage temperature (?) ?5 quiescent supply current (ma) 18 20 22 125 lt1103 g04 16 14 12 ?0 ?5 0 175 25 50 75 100 150 21 19 17 15 13 30v 8v input voltage (v) 0 0 shutdown supply current ( m a) 50 150 200 250 500 350 10 20 25 lt1103 g05 100 400 450 300 5 15 30 35 v c = 75mv v c = 0 v c (mv) 0 shutdown current ( m a) 300 400 500 160 lt1103 g06 200 100 0 40 80 120 200 50 150 250 350 450 20 60 100 140 180 25? 125? 55?
7 lt1103/LT1105 typical perfor m a n ce characteristics u w 5v reference voltage vs temperature temperature (?) ?5 5v reference voltage (v) 5.10 5.20 125 lt1103 g16 5.00 4.90 4.80 ?5 25 75 175 ?0 0 50 100 150 5.15 5.05 4.95 4.85 5v load regulation vs temperature temperature (?) ?5 5v line regulation (%/ v) 0.03 0.04 0.05 125 lt1103 g18 0.02 0.01 0 ?5 25 75 175 150 100 50 0 ?0 5v line regulation vs temperature 15v gate bias dropout voltage vs temperature 15v gate bias reference vs temperature temperature (?) ?5 13.8 15v gate bias reference (v) 14.2 14.6 15.0 15.4 15.8 16.2 ?5 25 75 125 lt1103 g20 175 ?0 0 50 100 150 5v reference short-circuit current vs temperature temperature (?) ?5 5v load regulation (%/ma) 0.015 0.020 0.025 125 lt1103 g17 0.010 0.005 0 ?5 25 75 175 150 100 50 0 ?0 temperature (?) ?5 15v gate bias dropout voltage (v) 1.5 2.0 2.5 125 lt1103 g21 1.0 0.5 0 ?5 25 75 175 150 100 50 0 ?0 temperature (?) ?5 ?.0 ovlo input bias current ( m a) ?.5 ?.0 ?.5 ?.0 ?.5 0 ?5 25 75 125 lt1103 g13 175 ?0 0 50 100 150 ovlo = 2v ovlo input bias current vs temperature soft-start charging current vs temperature temperature (?) ?5 0 soft-start charging current ( m a) 10 20 30 40 50 60 ?5 25 75 125 lt1103 g14 175 ?0 0 50 100 150 temperature (?) ?5 soft-start reset current (ma) 3 4 5 125 lt1103 g15 2 1 0 ?5 25 75 175 150 100 50 0 ?0 soft-start reset current vs temperature temperature ( c) ?5 5v reference short-circuit current (ma) 90 110 125 lt1103 g19 70 50 30 ?5 25 75 175 ?0 0 50 100 150 100 80 60 40
8 lt1103/LT1105 typical perfor m a n ce characteristics u w 15v gate bias short-circuit current vs temperature fb input bias current vs temperature (v c = 1v) change in fb input bias current with change in v c vs temperature (v c = 1v to 4v) temperature (?) ?5 feedback threshold (v) 4.52 4.56 4.60 125 lt1103 g25 4.48 4.44 4.40 ?5 25 75 175 150 100 50 0 ?0 feedback threshold vs temperature temperature (?) ?5 fb input bias current ( m a) 12 16 20 125 lt1103 g26 8 4 0 ?5 25 75 175 150 100 50 0 ?0 temperature (?) ?5 7 change in fb input bias current with change in v c ( m a/ v) 8 10 11 12 14 ?0 50 100 lt1103 g27 9 13 25 150 175 ?5 0 75 125 error amplifier voltage gain vs temperature error amplifier transconductance vs temperature temperature (?) ?5 error amplifier transconductance ( m mho) 25000 125 lt1103 g28 15000 10000 5000 ?5 25 75 175 ?0 0 50 100 150 20000 frequency (khz) 0.004 error amplifier transconductance (mho) 0.008 0.012 0.016 0.020 0.1 10 100 1000 lt1103 g29 0 1 0.018 0.014 0.010 0.006 0.002 40 80 120 160 200 0 180 140 100 60 20 phase (degrees) phase phase gm gm error amplifier transconductance and phase vs frequency temperature (?) ?5 error amplifier voltage gain (v/ v) 2500 125 lt1103 g30 1500 1000 500 ?5 25 75 175 ?0 0 50 100 150 2000 temperature (?) ?5 low switch drive lockout threshold (v) 9.9 10.2 10.5 125 lt1103 g23 9.6 9.3 9.0 ?5 25 75 175 150 100 50 0 ?0 low switch drive lockout threshold vs temperature high switch drive lockout threshold vs temperature temperature (?) ?5 17.0 high switch drive lockout threshold (v) 17.5 18.0 18.5 19.0 19.5 20.0 ?5 25 75 125 lt1103 g24 175 ?0 0 50 100 150 temperature ( c) ?5 15v gate bias short-circuit current (ma) 90 110 130 125 lt1103 g22 70 50 30 ?5 25 75 175 150 100 50 0 ?0
9 lt1103/LT1105 cc hara terist ics uw a t y p i ca lper f o r c e temperature (?) ?5 error amplifier source current ( m a) 350 125 lt1103 g31 250 200 150 ?5 25 75 175 ?0 0 50 100 150 300 325 275 225 175 error amplifier source current vs temperature lt1103 output switch leakage current vs temperature v c switching threshold voltage vs temperature error amplifier low clamp voltage vs temperature (fb = 4.75v) temperature (?) ?5 0.3 error amplifier low clamp voltage (v) 0.4 0.5 0.6 0.7 0.8 0.9 ?5 25 75 125 lt1103 g34 175 ?0 0 50 100 150 temperature (?) ?5 v c switching threshold (v) 1.1 1.3 1.5 125 lt1103 g35 0.9 0.7 0.5 ?5 25 75 175 150 100 50 0 ?0 temperature (?) ?5 lt1103 output switch leakage current ( m a) 120 160 200 125 lt1103 g36 80 40 0 ?5 25 75 175 150 100 50 0 ?0 v sw = 45v v sw = 15v lt1103 v sw current limit vs temperature temperature (?) ?5 lt1103 v sw current limit (a) 2.6 2.8 3.0 125 lt1103 g40 2.4 2.2 2.0 ?5 25 75 175 2.1 2.3 2.5 2.7 2.9 ?0 0 50 100 150 dc = 25% lt1103 v sw current limit vs duty cycle duty cycle (%) 0 0 lt1103 v sw current limit (a) 0.5 1.0 1.5 2.0 20 40 60 80 lt1103 g39 2.5 3.0 10 30 50 70 25? 125? ?5? lt1103 switch saturation voltage vs temperature temperature (?) ?5 0 lt1103 switch saturation voltage (v) 0.2 0.4 0.6 0.8 1.0 1.2 ?5 25 75 125 lt1103 g38 175 ?0 0 50 100 150 i sw = 1.5a i sw = 0.5a temperature (?) ?5 1.5 error amplifier sink current (ma) 2.0 2.5 3.0 3.5 4.0 4.5 ?5 25 75 125 lt1103 g32 175 ?0 0 50 100 150 error amplifier sink current vs temperature temperature (?) ?5 error amplifier high clamp voltage (v) 4.3 4.4 4.5 125 lt1103 g33 4.2 4.1 4.0 ?5 25 75 175 150 100 50 0 ?0 error amplifier high clamp voltage vs temperature (fb = 4v)
10 lt1103/LT1105 cc hara terist ics uw a t y p i ca lper f o r c e LT1105 v sw high saturation voltage vs temperature temperature (?) ?5 0 LT1105 v sw high saturation voltage (v) 0.5 1.0 1.5 2.0 2.5 3.0 ?5 25 75 125 lt1103 g43 175 ?0 0 50 100 150 i sw = 750ma i sw = 200ma temperature (?) ?5 lt1103 driver current (ma /a) 30 40 50 125 lt1103 g41 20 10 0 ?5 25 75 175 150 100 50 0 ?0 lt1103 driver current vs temperature LT1105 v sw low saturation voltage vs temperature temperature (?) ?5 0 LT1105 v sw low saturation voltage (v) 0.5 1.0 1.5 2.0 2.5 3.0 ?5 25 75 125 lt1103 g42 175 ?0 0 50 100 150 i sw = 750ma i sw = 200ma LT1105 current limit threshold voltage vs temperature LT1105 v sw rise time vs temperature LT1105 v sw fall time vs temperature temperature (?) ?5 300 LT1105 current limit threshold voltage (mv) 325 350 375 400 425 450 ?5 25 75 125 lt1103 g46 175 ?0 0 50 100 150 dc = 25? temperature (?) ?5 LT1105 v sw rise time (ns) 60 80 100 125 lt1103 g44 40 20 0 ?5 25 75 175 150 100 50 0 ?0 c load = 4700pf c load = 1000pf temperature (?) ?5 LT1105 v sw fall time (ns) 60 80 100 125 lt1103 g45 40 20 0 ?5 25 75 175 150 100 50 0 ?0 c load = 4700pf c load = 1000pf
11 lt1103/LT1105 pi n fu n ctio n s uuu lt1103 fb: the feedback pin is the inverting input to the sampling error amplifier. the noninverting input is tied to a 4.5v reference. the fb pin is used for output voltage sensing. the input bias current is a function of the control pin v c voltage and can be used for load regulation compensation by including a resistor in series with the fb pin. the sampling error amplifier has a typical g m of 0.012 mhos and the output of the sampling error amplifier has asym- metrical slew rate to reduce overshoot during start-up conditions or following the release of an output overload. v c : the v c control pin is used for frequency compensa- tion, current limiting and shutdown. it is the high imped- ance output of the sampling error amplifier and the input of the current limit comparator. gnd: the ground pin acts as both the negative sense point for the internal sampling error amplifier feedback signal and as the high current path for the 2a switch. also, the case of the 7-lead to-220 is connected to ground. proper connections to ground for signal paths and high current paths must be made in order to insure good load regulation. osc: the oscillator pin sets the operating frequency of the regulator with one external capacitor to ground. maximum duty cycle can also be adjusted by using an external resistor to alter the charge/discharge ratio. v in : the input supply pin is designed to operate with voltages of 12v to 30v. the supply current is typically 200 m a up to the start-up threshold of 16v. normal oper- ating supply current is fairly flat at 18ma down to the shutdown threshold of 7v. switching is inhibited for v in less than 12v due to the gate drive detection circuit. 15v: a 15v reference is used to bias the gate of an external power fet. the voltage temperature coefficient is typically 3mv/ c and the output can source 30ma. typical dropout voltage is 1.5v for v in less than 17v and 30ma of load current. v sw : the switch output pin is the collector of the internal npn power switch. this pin has a typical on resistance of 0.4 w and a minimum breakdown voltage of 50v. this pin also ties to the fet gate drive detection circuit. LT1105 all functions on the LT1105 are equivalent to the lt1103 with the exception of the v sw pin and the i lim pin and the availability of the ovlo, 5v, and ss functions. ovlo: the overvoltage lockout pin inhibits switching when the pin is pulled above its threshold voltage of 2.5v. ovlo is implemented with a resistor divider network from the rectified dc line and is used to protect the external fet from an overvoltage condition in the off state. this func- tion is only available on the 14-lead pdip. 5v: a 5v reference is available to power primary-side circuitry. the temperature coefficient is typically 50ppm/ c and the output can source 25ma. this func- tion is only available on the 14-lead pdip. ss: the soft-start pin is used to either program start-up time with a capacitor to ground or to set external current limit with a resistor divider. the ss pin has a 40 m a pull-up current and is reset to 0v by a 1ma pull-down current during start-up and shutdown. this function is only avail- able on the 14-lead pdip. v sw : the switch output pin is the output of a 1a npn totem-pole stage. the v sw pin turns the external fet on by pulling its gate high. break-before-make action of 200ns on each switch edge is built in to eliminate cross conduc- tion currents. i lim : the i lim pin is the input to the current limit amplifier and requires the use of a noninductive, power sense resistor from i lim to ground to set current limit. the typical current limit threshold voltage is 350mv. the typical input bias current is 100 m a out of the pin.
12 lt1103/LT1105 block diagra s w lt1103 + a v = 10 gate bias detect 15v gate bias sampling error amp g m = 0.012 overvoltage lockout 0.15v 2.5v 40 m a current limit amp 0.15 w 6v v sw osc start-up oscillator 15v v in 5v fb 0vlo 16v 7v 4.5v v c ss 5v v ref spike blank comp logic driver antisat + gnd lt1103 bd shut down reset
13 lt1103/LT1105 block diagra s w LT1105 + a v = 10 gate bias detect 15v gate bias sampling error amp g m = 0.012 overvoltage lockout 0.15v 2.5v reset 40 m a current limit amp 6v v sw osc start-up oscillator 15v v in 5v fb 0vlo 16v 7v 4.5v v c ss 5v v ref shut down spike blank comp logic + gnd LT1105 bd driver driver antisat i lim
14 lt1103/LT1105 u atio oper lt1103 the lt1103 is a current mode switcher. switch duty cycle is controlled by switch current rather than directly by the output voltage. referring to the block diagram, the switch is turned on at the start of each oscillator cycle. it is turned off when switch current reaches a predetermined level. control of output voltage is obtained by using the output of a voltage sensing error amplifier to set current trip level. this technique has several advantages. first, it has imme- diate response to input voltage variations, unlike ordinary switchers which have notoriously poor line transient response. second, it reduces the 90 phase shift at mid frequencies in the transformer. this greatly simplifies closed-loop frequency compensation under widely vary- ing input voltage or output load conditions. finally, it allows simple pulse-by-pulse current limiting to provide maximum switch protection under output overload or short-circuit conditions. a start-up loop with hysteresis allows the ic supply voltage to be bootstrapped from an extra primary side winding on the power transformer. from 0v to 16v on v in , the lt1103 is in a prestart mode and total input current is typically 200 m a. above 16v, up to 30v, the 6v regulator that biases the internal circuitry and the externally avail- able 15v regulator is turned on. the internal circuitry remains biased on until v in drops below 7v and the part returns to the prestart mode. output switching stops when the v sw drive is less than 10v corresponding to v in of about 12v. the oscillator provides the basic clock for all internal timing. frequency is adjustable to 200khz with one exter- nal capacitor from osc to ground. the oscillator turns on the output switch via the logic and driver circuitry. adap- tive antisat circuitry detects the onset of saturation in the power switch and adjusts driver current instantaneously to limit switch saturation. this minimizes driver dissipa- tion and provides very rapid turn-off of the switch. the lt1103 is designed to drive the source of an external power fet in common gate configuration. the 15v regu- lator biases the gate to guarantee the fet is on when the switch is on. special drive detection circuitry senses the gate bias voltage and prevents the output switch from turning on if the gate voltage is less than 10v or greater than 20v, the industry standards for power mosfet operation. the switch current is sensed internally and amplified to trip the comparator and turn off the switch according to the v c pin control voltage. a blanking circuit suppresses the output of the current limit comparator for 500ns at the beginning of each switch cycle. this prevents false trip- ping of the comparator due to current spikes caused by external parasitic capacitance and diode stored charge. the 4.5v zener-based reference biases the positive input of the sampling error amplifier. the negative input (fb) is used for output voltage sensing. the sampling error amplifier allows the lt1103 to operate in fully isolated flyback mode by regulating from the flyback voltage of the bootstrap winding. the leakage inductance spike at the leading edge of the flyback waveform is ignored with a blanking circuit. the flyback waveform is directly propor- tional to the output voltage in a transformer-coupled flyback topology. output voltages are fully floating up to the breakdown voltage of the transformer windings. mul- tiple floating outputs are easily obtained with additional windings. the error signal developed at the comparator input is brought out externally. this v c pin has three functions including frequency compensation, current limit adjust- ment and total regulator shutdown. during normal opera- tion, this pin sits at a voltage between 1.2v (low output current) and 4.4v (high output current). the error ampli- fier is a current output (g m ) type, so this voltage can be externally clamped for adjusting current limit. switch duty cycle goes to zero if the v c pin is pulled to ground through a diode, placing the lt1103 in an idle mode. pulling the v c pin below 0.15v causes total regulator shutdown and places the lt1103 in a prestart mode. LT1105 the LT1105 is a current mode switcher. switch duty cycle is controlled by switch current rather than directly by output voltage. referring to the block diagram, the switch is turned on at the start of each oscillator cycle. it is turned off when switch current reaches a predetermined level.
15 lt1103/LT1105 u atio oper control of output voltage is obtained by using the output of a voltage sensing error amplifier to set current trip level. this technique has several advantages. first, it has imme- diate response to input voltage variations, unlike ordinary switchers which have notoriously poor line transient re- sponse. second, it reduces the 90 phase shift at midfrequencies in the transformer. this greatly simplifies closed-loop frequency compensation under widely vary- ing input voltage or output load conditions. finally, it allows simple pulse-by-pulse current limiting to provide maximum switch protection under output overload or short-circuit conditions. a start-up loop with hysteresis allows the ic supply voltage to be bootstrapped from an extra primary side winding on the power transformer. from 0v to 16v on v in , the LT1105 is in prestart mode and total input current is typically 200 m a. above 16v, up to 30v, the 6v regulator that biases the internal circuitry and the externally avail- able 5v and 15v regulators are turned on. the internal circuitry remains biased on until v in drops below 7v and the part returns to prestart mode. output switching stops when the 15v gate bias reference is less than 10v corre- sponding to v in of about 12v. the oscillator provides the basic clock for all internal timing. frequency is adjustable to 200khz with one exter- nal capacitor from osc to ground. the oscillator turns on the output switch via the logic and driver circuitry. the LT1105 is designed to drive the gate of an external power fet in common source configuration. the drivers and the 1a maximum totem-pole output stage are biased from the 15v gate bias reference. special drive detection circuity senses the gate bias reference voltage and pre- vents the output switch from turning on if this voltage is less than 10v or greater than 20v. break-before-make action of 200ns is built into each switch edge to eliminate cross conduction currents. switch current is sensed externally through a precision, power resistor. this allows for greater flexibility in switch current and output power than allowed by the lt1103. the voltage across the sense resistor is fed into the i lim pin and amplified to trip the comparator and turn off the switch according to the v c pin control voltage. a blanking circuit suppresses the output of the current limit comparator for 500ns at the beginning of each switch cycle. this prevents false tripping of the comparator due to current spikes caused by external parasitic capacitance and diode stored charge. a 4.5v zener-based reference biases the positive input of the sampling error amplifier. the negative input (fb) is used for output voltage sensing. the sampling error amplifier allows the LT1105 to operate in fully isolated flyback mode by regulating the flyback voltage of the bootstrap winding. the leakage inductance spike at the leading edge of the flyback waveform is ignored with a blanking circuit. the flyback waveform is directly propor- tional to the output voltage in the transformer coupled flyback topology. output voltages are fully floating up to the breakdown voltage of the transformer windings. mul- tiple floating outputs are easily obtained with additional windings. the error signal developed at the comparator input is brought out externally. the v c pin has three functions including frequency compensation, current limit adjust- ment and total regulator shutdown. during normal opera- tion, this pin sits at a voltage between 1.2v (low output current) and 4.4v (high output current). the error ampli- fier is a current output (g m ) type, so this voltage can be externally clamped for adjusting current limit. switch duty cycle goes to zero if the v c pin is pulled to ground through a diode, placing the LT1105 in an idle mode. pulling the v c pin below 0.15v causes total regulator shutdown and places the LT1105 in prestart mode. the ss pin implements soft-start with one external capaci- tor to ground. the internal pull-up current and clamp transistor limit the voltage at v c to one diode drop above the voltage at the ss pin, thereby controlling the rate of rise of switch current in the regulator. the ss pin is reset to 0v when the LT1105 is in prestart mode. a final protection feature includes overvoltage lockout monitoring of the main supply voltage on the ovlo pin. if the ovlo pin is greater than 2.5v, the output switch is prevented from turning on. this function can be disabled by grounding the ovlo pin.
16 lt1103/LT1105 bootstrap start it is inefficient as well as impractical to power a switching regulator control ic from the rectified dc input as this voltage is several hundred volts. self-biased switching regulator topologies take advantage of a lower voltage auxiliary winding on the power transformer or inductor to power the regulator, but require a start-up cycle to begin regulation. start-up circuitry with hysteresis built into the lt1103/ LT1105 allows the input voltage to increase from 0v to 16v before the regulator tries to start. during this time the start-up current of the switching regulator is typically 200 m a and all internal voltage regulators are off. the low quiescent current allows the input voltage to be trickled up with only 500 m a of current from the rectified dc line voltage, thereby minimizing power dissipation in the start- up resistor. at 16v, the internal voltage regulators are turned on and switching begins. if enough power feeds back through the auxiliary winding to keep the input voltage to the switching regulator above 12v, then switching continues and a bootstrap start is accomplished. if the input voltage drops below 12v, then the fet drive detection circuit locks out switching. the input voltage continues to fall as the v in bypass capacitor is discharged by the normal quiescent current of the lt1103/LT1105. once the input voltage falls below 7v, the internal voltage regulators are turned off and the switching regulator returns to the low start-up current state. a continuous burp start mode indicates a fault condition or an incomplete power loop. the trickle current required to bootstrap the regulator input voltage is typically generated with a resistor from the rectified dc input voltage. when combined with the regulator input bypass capacitor, the start-up resistor creates a ramp whose slope governs the turn-on time of the regulator as well as the period of the burp start mode. the design trade-offs are power dissipated in the trickle resistor, the turn-on time of the regulator, and the hold-up time of the regulator input bypass capacitor. the value of the start-up resistor is set by the minimum rectified dc input voltage to guarantee sufficient start-up current. the recommended minimum trickle current is 500 m a. the power rating of the start-up resistor is set by the maximum rectified dc input voltage. a final consideration for the start-up resistor is to insure that the maximum voltage rating of the resistor is not exceeded. typical carbon film resistors have a voltage rating of 250v. the most reliable and economical solution for the start-up resistor is generally provided by placing several 0.25w resistors in series. the lt1103/LT1105 is designed to operate with supply pin voltages up to 30v. however, the auxiliary bias winding should be designed for a typical output voltage of 17v to minimize ic power dissipation and efficiency loss. allowances must also be made for cross regulation of the bias voltage due to variations in the rectified dc line voltage and output load current. soft-start soft-start refers to the controlled increase of switch current from a start-up or shutdown state. this allows the power supply to come up to voltage in a controlled manner and charge the output capacitor without activating current limit. in general, soft-start is not required on the LT1105 due to the design of the sampling error amplifier g m stage which generates asymmetrical slew capability on the v c pin. this feature exhibits itself as a typical 3ma sink current capability on the v c pin whereas source current is only 275 m a. the low g m of the error amplifier allows small- valued compensation capacitors to be used on v c . this allows the sink current to slew the compensation capacitor quickly. therefore, overshoot of the output voltage on start-up sequences and recovery from overload or short- circuit conditions is prevented. however, if a longer start- up period is required, the soft-start function can be used. soft-start is implemented with an internal 40 m a pull-up and a transistor clamp on the v c pin so that a single external capacitor from ss ground can define the linear ramp function. the voltage at v c is limited to one v be above the soft-start pin (ss). the time to maximum switch current is defined as the capacitance on ss multiplied by the active range in volts of the v c pin divided by the pull- up current: t c (3.2v) 40 a = m applicatio n s i n for m atio n wu u u
17 lt1103/LT1105 ground (lt1103) the ground pin of the lt1103 is important because it acts as the negative sense point for the internal error amplifier feedback signal, the negative sense point for the current limit amplifier, and as the high current path for the 2a switch. the tab of the 7-lead to-220 is internally connected to gnd (pin 4). to avoid degradation of load regulation, the feedback resistor divider string and the reference side of the bias winding should be directly connected to the ground pin on the package. these ground connections should not be mixed with high current carrying ground return paths. the length of the switch current ground path should be as short as possible to the input supply bypass capacitor and low resistance for best performance. the case of the lt1103 package is desirable to use as the high current ground return path as this is a lower resistive and inductive path than that of the actual package pin and will help minimize voltage spikes associated with the high di/dt switch current. avoiding long wire runs to the ground pin minimizes load regulation effects and inductive voltages created by the high di/dt switch current. ground plane techniques should also be used and will help keep emi to a minimum. grounding techniques are illustrated in the typical applications section. ground (LT1105) the ground pin of the LT1105 is important because it acts as the negative sense point for the internal error amplifier feedback signal and as the negative sense point for the current limit amplifier. the LT1105 8-pin pdip has pin 1 as its ground. the LT1105 14-pin pdip has pin 1 and pin 7 as grounds and must be tied together for proper operation. to avoid degradation of load regulation, the feedback resistor divider should be directly connected to the package ground pin. these ground connections should not be mixed with high current carrying ground return paths. the length of the switch current ground path should be as short as possible to the input supply bypass capacitor and ss is reset to 0v whenever v in is less than 7v (prestart mode) or when shutdown is activated by pulling v c below 0.15v. the ss pin has a guaranteed reset sink current of 1ma when either the regulator supply voltage v in falls below 7v or the regulator is placed in shutdown. shutdown the lt1103/LT1105 can be put in a low quiescent current shutdown mode by pulling v c below 150mv. in the shutdown mode the internal voltage regulators are turned off, ss is reset to 0v and the part draws less than 200 m a. to initiate shutdown, about 400 m a must be pulled out of v c until the internal voltage regulators turn off. then, less than 50 m a pull-down current is required to maintain shutdown. the shutdown function has about 60mv of hysteresis on the v c pin before the part returns to normal operation. soft-start, if used, controls the recovery from shutdown. 5v reference a 5v reference output is available for the users convenience to power primary-side circuitry or to generate a clamp voltage for switch current limiting. the output will source 25ma and the voltage temperature coefficient is typically 50ppm/ c. if bypassing of the 5v reference is required, a 0.1 m f is recommended. values of capacitance greater than 1 m f may be susceptible to ringing due to decreased phase margin. in such cases, the capacitive load can be isolated from the reference output with a small series resistor at the expense of load regulation performance. overvoltage lockout the switching supply and primarily the external power mosfet can be protected from an extreme surge of the input line voltage with the overvoltage lockout feature implemented on the ovlo pin. if the voltage on ovlo rises above its typical threshold voltage of 2.5v, output switching is inhibited. this feature can be implemented with a resistive divider off of the rectified dc input voltage. this feature is only available on the LT1105 in the 14-lead pdip and must be tied to ground if left unused. applicatio n s i n for m atio n wu u u
18 lt1103/LT1105 note that the capacitor value must change to maintain the same frequency. for example, a 24k resistor from 5v to osc and a 440pf capacitor from osc to ground will yield 100khz with 50% maximum duty cycle. a 56k resistor and a 280pf capacitor from osc to ground will yield 100 khz with 80% maximum duty cycle. the oscillator can be synchronized to an external clock by coupling a sync pulse into the osc pin. the width of this pulse should be a minimum of 500ns. the oscillator can only be synchronized up in frequency and the synchronizing frequency must be greater than the maximum possible unsynchronized frequency (for the chosen oscillator capacitor value). the amplitude of the sync pulse must be chosen so that the sum of the oscillator voltage amplitude plus the sync pulse amplitude does not exceed the 6v bias reference. otherwise, the oscillator pull-up current source will saturate and erroneous operation will result. if the lt1103/LT1105 is positioned on the primary side of the transformer and the external clock on the isolated secondary output side, the sync signal must be coupled into the osc pin using a pulse transformer. the pulse transformer must meet all safety/isolation requirements as it also crosses the isolation boundary. an example of externally synchronizing the oscillator is shown in the typical applications section. gate biasing (lt1103) the lt1103 is designed to drive an external power mosfet in the common gate or cascode connection with the v sw pin. the advantage is that the switch current can be sensed internally, eliminating a low value, power sense resistor. the gate needs to be biased at a voltage high enough to guarantee that the fet is saturated when the open-collector source drive is on. this means 10v as specified in fet data sheets, plus 1v for the typical switch saturation voltage, plus a couple of volts for temperature variations and processing tolerances. this leads to 15v for a practical gate bias voltage. power mosfets are well suited to switching power supplies because their high speed switching characteristics promote high switching efficiency. to achieve high switching speed, low resistance for best performance. this will help minimize voltage spikes associated with the high di/dt switch current. avoiding long wire runs to the ground pin minimizes load regulation effects and inductive voltages created by the high di/dt switch current. ground plane techniques should also be used and will help keep emi to a minimum. grounding techniques are illustrated in the typical applications section. oscillator the oscillator of the lt1103/LT1105 is a linear ramp type powered from the internal 6v bias line. the charging currents and voltage thresholds are generated internally so that only one external capacitor is required to set the frequency. the 150 m a pull-up current, which is on all the time, sets the preset maximum on-time of the switch and the 450 m a pull-down current which is turned on and off, sets the dead time. the threshold voltages are typically 2v and 4.5v, so for a 400pf capacitor the ramp-up time of the voltage on the osc pin is 6.67 m s and the ramp-down time is 3.3 m s, resulting in an operating frequency of 100khz. although the oscillator, as well as the rest of the switching regulator, will function at higher frequencies, 200khz is the practical upper limit that will allow control range for line and load regulation. the lowest operating frequency is limited by the sampling error amplifier to about 10khz. the frequency temperature coefficient is typically C80ppm/ c with a good low t.c. capacitor. this means that with a low temperature coefficient capacitor, the temperature coefficient of the currents and the temperature coefficient of the thresholds sum to C80ppm/ c over the commercial temperature range. bowing in the temperature coefficient of the currents affects the frequency about 3% at the extremes of the military temperature range. the capacitor type chosen will have a direct effect on the frequency tempco. maximum duty cycle is set internally by the pull-up and pull-down currents, independent of frequency. it can be adjusted externally by modifying the fixed pull-up current with an additional resistor. in practice, one resistor from the osc pin to the 5v reference or to ground does the job. applicatio n s i n for m atio n wu u u
19 lt1103/LT1105 keep the switch just at the edge of saturation. very low switch current results in nearly zero driver current and high switch currents automatically increase driver current as necessary. the ratio of switch current to driver current is approximately 30:1. this ratio is determined by the sizing of the extra emitter and the value of the current source feeding the driver circuitry. the quasisaturation state of the switch permits rapid turn-off without the need for reverse base emitter voltage drive. gate biasing (LT1105) the LT1105 is designed to drive an external power mosfet in the common source configuration with the totem-pole output v sw pin. the advantage is added switch current flexibility (limited only by the choice of external power fet) and higher output power applications than allowed by lt1103. an external, noninductive, power sense resistor must be used in series with the source of the fet to detect switch current and must be tied to the input of the current limit amplifier. the gate needs to be biased at a voltage high enough to guarantee that the fet is saturated when the totem-pole gate drive is on. this means 10v as specified in fet data sheets, plus the totem-pole high side saturation voltage plus a couple of volts for temperature variations and processing tolerances. this leads to 15v for a practical gate bias voltage. power mosfets are well suited to switching power supplies because their high speed switching characteristics promote high switching efficiency. to achieve high switching speed, the gate capacitance must be charged and discharged quickly with high peak currents. in particular, the turn-off current can be as high as the peak switch current. the switching speed is controlled by the impedance seen by the gate capacitance. practically speaking, zero impedance is not desirable because of the high frequency noise spikes introduced to the system. the gate bias supply which drives the totem-pole output stage should be bypassed with a 1 m f low esr capacitor to ground. this capacitor supplies the energy to charge the gate capacitance during gate drive turn-on. the power mosfet should have a 5 w resistor or larger in series with its gate from the v sw pin to define the source impedance. a special circuit in the lt1103 senses the voltage at v sw prior to turning on the switch. v sw is tied to the source of the fet and should represent the bias voltage on the gate when the switch is off. when the switch first turns off, the drain flies back until it is clamped by a snubber network. the source also flies high due to parasitic capacitive coupling on the fet and parasitic inductance of the leads. an extra diode from the source to the gate or v in will provide insurance against fault conditions that might otherwise damage the fet. the diode clamps the source to one diode drop above the gate or v in , thereby limiting the gate source reverse bias. once the energy in the leakage inductance spike is dissipated and the primary is being regulated to its flyback voltage, the diode shuts off. the source is then floating and its voltage will be close to the gate voltage. if the sensed voltage on v sw is less than 10v or greater than 20v, the circuit prevents the switch from turning on. this protects the fet from dissipating high power in a nonsaturated state or from excessive gate- source voltage. the oscillator continues to run and the net effect is to skip switching cycles until the gate bias voltage is corrected. one consequence of the gate bias detection circuit is that the start-up window is 6v if the gate is biased from v in and to 4v if the gate is biased from the 15v output. this influences the size of the bypass capacitor on v in . v sw output (lt1103) the v sw pin of the lt1103 is the collector of an internal npn power switch. this npn has a typical on resistance of 0.4 w and a typical breakdown voltage (bv cbo ) of 75v. fast switching times and high efficiency are obtained by using a special driver loop which automatically adapts base drive current to the minimum required to keep the switch in a quasisaturated state. the key element in the loop is an extra emitter on the output power transistor as seen in the block diagram. this emitter carries no current when the npn output transistor collector is high (unsaturated). in this condition, the driver circuit can deliver very high base drive to the switch for fast turn-on. when the switch saturates, the extra emitter acts as a collector of an npn operating in inverted mode and pulls base current away from the driver. this linear feedback loop serves itself to applicatio n s i n for m atio n wu u u
20 lt1103/LT1105 the LT1105 provides a 15v regulated output intended for driving the totem-pole output stage. it will source 30ma into a capacitive load with no stability problems. the output voltage temperature coefficient is 3mv/ c. if v in drops below 17v, the 15v output follows about 2.0v below v in until the part shuts down. if the 15v output is pulled above 17.5v, it will sink 5ma. a special circuit in the LT1105 senses the voltage at the 15v regulated output prior to turning on the switch. the 15v regulator drives the totem-pole output stage and the v sw pin will pull the gate of the fet very close to the value of the 15v output when v sw turns on. therefore, the 15v output represents what the gate bias voltage on the fet will be when the fet is turned on. if the sensed voltage on the 15v output is less than 10v or greater than 20v, the circuit prevents the switch from turning on. this protects the fet from dissipating high power in a nonsaturated state or from excessive gate-source voltage. the oscillator continues to run and the net effect is to skip switching cycles until the gate bias voltage is corrected. one consequence of the gate bias detection circuit is that the start-up window is 4v. this influences the size of the bypass capacitor on v in . v sw output (LT1105) the v sw pin of the LT1105 is the output of a 1a totem-pole driver stage. this output stage turns an external power mosfet on by pulling its gate high. break-before-make action of 200ns is built into each switch edge to eliminate cross-conduction currents. fast switching times and high efficiency are obtained by using a low loss output stage and a special driver loop which automatically adapts base drive current to the totem-pole low side drive. the key element in the loop is an extra emitter on the output pull- down transistor as seen in the block diagram. this emitter carries no current when the low side transistor collector is high (unsaturated). in this condition, the driver can deliver very high base drive to the output transistor for fast turn-off. when the low side transistor saturates, the extra emitter acts as a collector of an npn operating in inverted mode and pulls base current away from the driver. this linear feedback loop serves itself to keep the switch just at the edge of saturation. this results in nearly zero driver current. the quasisaturation state of the low side switch permits rapid turn-on of the external fet when v sw pulls high. fully isolated flyback mode a unique sampling error amplifier included in the control loop of the lt1103/LT1105 eliminates the need for an optoisolator while providing 1% line and load regulation in a magnetic flux-sensed flyback converter. in this mode, the flyback voltage on the primary during switch off time is sensed and regulated. it is difficult to derive a feedback signal directly from the primary flyback voltage as this voltage is typically several hundred volts. a dedicated winding is not required because the bias winding for the regulator lends itself to flux-sensing. flux-sensing made practical simplifies the design of off line power supplies by minimizing the total number of external components and reduces the components which must cross the isolation barrier to one, the transformer. this inherently implies greater safety and reliability. the transformer must be optimized for coupling between the bias winding and the secondary output winding(s) while maintaining the required isolation and minimizing the parasitic leakage inductances. although magnetic flux-sensing has been used in the past, the technique has exhibited poor output voltage regulation due to the parasitics present in a transformer coupled design. transformers which provide the safety and isolation as required by various international safety/regulatory agencies also provide the poorest output voltage regulation. solutions to these parasitic elements have been achieved with the novel sampling error amplifier of the lt1103/ LT1105. a brief review of flyback converter operation and the problems which create a poorly regulated output will provide insight on how the sampling error amplifier of the lt1103/LT1105 addresses the regulation issue of magnetic flux sensed converters. the following figure shows a simplified diagram of a flyback converter using magnetic flux sensing. the major parasitic elements present in the transformer coupled design are indicated. the relationships between the primary applicatio n s i n for m atio n wu u u
21 lt1103/LT1105 to zero or changing polarity. therefore, the voltage on the bias winding is only valid as a representation of the output voltage while the secondary is delivering current. although the bias winding flyback voltage is a representa- tion of the output voltage, its voltage is not constant. for a brief period following the leakage inductance spike, the bias winding flyback voltage decreases due to nonlinearities and parasitics present in the transformer. following this nonlinear behavior is a period where the bias winding flyback voltage decreases linearly. this behavior is easily explained. current flow in the secondary decreases lin- early at a rate determined by the voltage across the secondary and the inductance of the secondary. the parasitic secondary leakage inductance appears as an impedance in series with the secondary winding. in addi- tion, parasitic resistances exist in the secondary winding, the output diode and the output capacitor. these imped- ances can be combined to form a lumped sum equivalent and which cause a voltage drop as secondary current flows. this voltage drop is coupled from the secondary to the bias winding flyback voltage and becomes more sig- nificant as the output is loaded more heavily. this voltage drop is largest at the beginning of switch off time and smallest just prior to either all transformer energy being depleted or the switch turning on again. the best representation of the output voltage is just prior to either all transformer energy being used up and the bias winding voltage collapsing to zero or just prior to the switch turning on again and the bias winding going negative. this point in time also represents the smallest forward voltage for the output diode. it is possible to redefine the relationship between the secondary winding voltage and the bias winding voltage as: v vvfir n1 bias out p = ++ () where vf is the forward voltage of the output diode, i is the current flowing in the secondary, r p is the lumped sum equivalent secondary parasitic impedance and n1 is the transformer turns ratio from the secondary to the bias winding. it is apparent that even though the above point in applicatio n s i n for m atio n wu u u voltage, the secondary voltage, the bias voltage and the winding currents are indicated in the figures found on the following page for both continuous and discontinuous modes of operation. simplified flyback converter d1 1:n lt1103 ai01 v bias s1 r l(lk sec ) v out c1 common l(ik pri ) v in 1:n1 n = turns ratio from secondary to primary. n1 = turns ratio from secondary to bias. n2 = n/n1 l(lk pri ) = primary leakage inductance. l(lk sec ) = secondary leakage inductance. r = parasitic winding, diode and output capacitor resistance. when the switch turns on, the primary winding sees the input voltage and the secondary and bias windings go to negative voltages as a function of the turns ratio. current builds in the primary winding as the transformer stores energy. when the switch turns off, the voltage across the switch flies back to a clamp level as defined by a snubber network until the energy in the leakage induc- tance of the primary dissipates. leakage inductance is one of the main parasitic elements in a flux-sensed converter and is modeled as an inductor in series with the primary and secondary of the transformer. these parasitic induc- tances contribute to changes in the bias winding voltage and thus the output voltage with increasing load current. the energy stored in the transformer transfers through the secondary and bias windings during switch off time. ideally, the voltage across the bias winding is set by the dc output voltage, the forward voltage of the output diode, and the turns ratio of the transformer after the energy in the leakage inductance spike of the primary is dissipated. this relationship holds until the energy in the transformer drops to zero (discontinuous mode) or the switch turns on again (continuous mode). either case results in the volt- age across the secondary and bias windings decreasing
22 lt1103/LT1105 flyback waveform for discontinuous mode operation flyback waveform for continuous mode operation v zener area ??= area ??to maintain zero volts across primary [v out + vf + (i sec ?r p )]/n v in 0v primary switch voltage area ??= area ??to maintain zero volts across secondary [v out + vf + (i sec ?r p )] 0v n ?v in secondary winding voltage [v out + vf + (i sec ?r p )]/n1 0v bias winding voltage area ??= area ??to maintain zero volts across bias winding n2 ?v in a b c d e f d i i pri primary current 0a i sec = i pri /n secondary current 0a i pri d i 0a switch current i pri snubber diode current 0a d t = (i pri )[l(lk pri )]/ v snub a b v zener area ??= area ??to maintain zero volts across primary [v out + vf + (i sec ?r p )]/ n v in 0v primary switch voltage area ??= area ??to maintain zero volts across secondary [v out + vf + (i sec ?r p )] 0v n ?v in secondary winding voltage [v out + vf + (i sec ?r p )]/ n1 0v bias winding voltage area ??= area ??to maintain zero volts across bias winding n2 ?v in e f d i d i i pri snubber diode current 0a i pri primary current 0a i sec = i pri /n secondary current 0a i pri 0a switch current lt1103 wf01 d t = (i pri )[l(lk pri )]/ v snub c d applicatio n s i n for m atio n wu u u
23 lt1103/LT1105 time is the most accurate representation of the output voltage, the answer given by the bias winding voltage is still off from the true answer by the amount i?r p /n1. the sampling error amplifier of the lt1103/LT1105 pro- vides solutions to the errors associated with the bias winding flyback voltage. the error amplifier is comprised of a leakage inductance spike blanking circuit, a slew rate limited tracking amplifier, a level detector, a sample-and- hold, an output g m stage and load regulation compensa- tion circuitry. this all seems complicated at first glance, but its operation is straightforward and transparent to the user of the ic. when viewed from a system or block level, the sampling error amplifier behaves like a simple transcon- ductance amplifier. heres how it works. the sampling error amplifier takes advantage of the fact that the voltage across the bias winding during at least a portion of switch off time is proportional to the dc output voltage of the secondary winding. the feedback network used to sense the bias winding voltage is no longer comprised of a traditional peak detector in conjunction with a resistor divider network. the feedback network consists of a diode in series with the bias winding feeding the resistor divider network directly. the resultant error signal is then fed into the input of the error amplifier. the purpose of the diode in series with the bias winding is now not to peak detect, but to prevent the fb pin (input of the error amplifier) from being pulled negative and forward biasing the substrate of the ic when the bias winding changes polarity with switch turn-on. the primary winding leakage inductance spike effects are first eliminated with an internal blanking circuit in the lt1103/LT1105 which suppresses the input of the fb pin for 1.5 m s at the start of switch off time. this prevents the primary leakage inductance spike from being propagated through the error amplifier and affecting the regulated output voltage. with the effects of the leakage inductance spike elimi- nated, the effects of decreasing bias winding flyback voltage can be addressed. with the traditional diode/ capacitor peak detector circuitry eliminated from the feed- back network, the tracking amplifier of the lt1103/LT1105 applicatio n s i n for m atio n wu u u follows the flyback waveform as it changes with time and amplifies the difference between the flyback signal and the internal 4.5v reference. tracking is maintained until the point in time where the bias winding voltage collapses as a result of all transformer energy being depleted (discon- tinuous mode) or the switch turning on again (continuous mode). the level detector circuit senses the fact that the bias winding flyback voltage is no longer a representation of the output voltage and activates an internal peak detec- tor. this effectively saves the most accurate representa- tion of the output voltage which is then buffered to the second stage of the error amplifier. the second stage of the error amplifier consists of a sample-and-hold. when the switch turns on, the sample- and-hold samples the buffered error voltage for 1 m s and then holds for the remainder of the switch cycle. this held voltage is then processed by the output g m stage and converted into a control signal at the output of the error amplifier, the v c pin. the final adjustment in regulation is provided by the load regulation compensation circuitry. as stated earlier, out- put regulation degrades with increasing load current (out- put power). the effect is traced to secondary leakage inductance and parasitic secondary winding, diode and output capacitor resistances. even though the tracking amplifier has obtained the most accurate representation of the output voltage, its answer is still flawed by the amount of the voltage drop across the secondary parasitic lumped sum equivalent impedance which is coupled to the bias winding voltage. this error increases with increasing load current. therefore, a technique for sensing load current conditions has been added to the lt1103/LT1105. the switch current is proportional to the load current by the turns ratio of the transformer. a small current proportional to switch current is generated in the lt1103/LT1105 and fed back to the fb pin. this allows the input bias current of the sampling error amplifier to be a function of load current. a resistor in series with the fb pin generates a linear increase in the effective reference voltage with increasing load current. this translates to a linear increase in output voltage with increasing load current. by adjust- ing the value of the series resistor, the slope of the load
24 lt1103/LT1105 applicatio n s i n for m atio n wu u u compensation can be set to cancel the effects of these parasitic voltage drops. the feature can be ignored by eliminating the series resistor and lowering the equivalent divider impedance to swamp out the effects of the input bias current. frequency compensation in order to prevent a regulator loop using the lt1103/ LT1105 from oscillating, frequency compensation is required. although the architecture of the lt1103/LT1105 is simple enough to lend itself to a mathematical approach to frequency compensation, the added complication of input/or output filters, unknown capacitor esr, and gross operating point changes with input voltage and load current variations all suggest a more practical empirical approach. many hours spent on breadboards have shown that the simplest way to optimize the frequency compensation of the lt1103/LT1105 is to use transient response techniques and an rc box to quickly iterate toward the final compensation network. additional information on this technique of frequency compensation can be found in linear technologys application note 19. in general, frequency compensation is accomplished with an rc series network on the v c pin. the error amplifier has a g m (voltage in to current out) of ? 12000 m mhos. voltage gain is determined by multiplying g m times the total equivalent error amplifier output loading, consisting of the error amplifier output impedance in parallel with the series rc external frequency compensation network. at dc, the external rc can be ignored. the output impedance of the error amplifier is typically 100k w resulting in a voltage gain of ? 1200v/v. at frequencies just above dc, the voltage gain is determined by the external compensation, r c and c c . the gain at mid frequencies is given by: a g 2fc v m c = p the gain at high frequencies is given by: a v = g m ? r c phase shift from the fb pin to the v c pin is 90 at mid frequencies where the external c c is controlling gain, then drops back to 0 (actually 180 since fb is an inverting input) when the reactance of c c is small compared to r c . thus, this rc series network forms a pole-zero pair. the pole is set by the high impedance output of the error amplifier and the value of c c on the v c pin. the zero is formed by the value of c c and the value of r c in series with c c on the v c pin. the rc series network will have capacitor values in the range of 0.1 m f to 1.0 m f and series resistor values in the range of 100 w to 1000 w . it is noted that the rc network on the v c pin forms the main compensation network for the regulator loop. however, if the load regulation compensation feature is used as ex- plained in the section on fully-isolated flyback mode, additional frequency compensation components are re- quired. the load regulation compensation feature involves the use of local positive feedback from the v c pin to the fb pin. thus, it is possible to add enough load regulation compensation to make the loop oscillate. in order to prevent oscillation, it is necessary to roll off this local positive feedback at high frequencies. this is accom- plished by placing a capacitor in parallel with the compen- sation resistor which is in series with the fb pin. a value for this capacitor in the range of 0.01 m f to 0.1 m f is recommended. the time constant associated with this rc combination will be longer than that associated with the loop bandwidth. thus, transient response will be affected in that settling time will be increased. however, this is typically not as important as controlling the absolute under or overshoot amplitude of the system in response to load current changes which could cause deleterious sys- tem operation. switching regulator topologies two basic switching regulator topologies are pertinent to the lt1103/LT1105, the flyback and forward converter. the flyback converter employs a transformer to convert one voltage to either a higher or lower output voltage. v out in continuous mode is defined as: vvn dc (1 dc) out in =
25 lt1103/LT1105 where n is the transformer turns ratio of secondary to primary and dc is the duty cycle. this formula can be rewritten in terms of duty cycle as: dc = v vnv out out in + () it is important to define the full range of input voltage, the range of output loading conditions and the regulation requirements for a design. duty cycle should be calculated for both minimum and maximum input voltage. in many applications, n can vary over a wide range without degrading performance. if maximum output power is desired, n can be optimized: n= vvf vv v opt out m in max snub () () + () where vf = forward voltage of the output diode v m = maximum switch voltage v snub = snubber clamp level C primary flyback voltage. in the isolated flyback mode, the lt1103/LT1105 sense and regulate the transformer primary voltage v pri during switch off time. the secondary output voltage will be regulated if v pri is regulated. v pri is related to v out by: v= vvf n pri out + () this allows duty cycle for an isolated flyback converter to be rewritten as: dc = duty cycle = v vv pri pri in + () an important transformer parameter to be determined is the primary inductance l pri . the value of this inductance is a trade-off between core size, regulation requirements, leakage inductance effects and magnetizing current d i. magnetizing current is the difference between the primary current at the start of switch on time and the current at applicatio n s i n for m atio n wu u u the end of switch on time. if maximum output power is needed, a reasonable starting value is found by assigning d i a value of 20% of the peak switch current (2a for the lt1103 and set by the external fet rating used with the LT1105). with this design approach, l pri is defined as: l v ( i)(f) 1 v v pri in in pri = + ? ? ? ? d if maximum output power is not required, then d i can be increased which results in lower primary inductance and smaller magnetics. maximum output power with an isolated flyback converter is defined by the primary flyback voltage and the peak allowed switch current and is limited to: p v vv vi i 2 ip re out(max) pri pri in in p 2 = () + () ? ? ? ? () ? ? d where r = total switch on resistance i p = maximum switch current e = overall efficiency ? 75% peak primary current is used to determine core size for the transformer and is found from: i vi vv ev v i 2 pri out out pri in pri in = ()() + () ()() + d a second consideration on primary inductance is the transition point from continuous mode to discontinuous mode. at light loads, the flyback pulse across the primary will drop to zero before the end of switch off time. the load current at which this starts to occur can be calculated from: i vv vv2vfl out(transition) pri in 2 pri in 2 out pri = () + ()()()() the forward converter as shown below is another transformer-based topology that converts one voltage to either a higher or a lower voltage.
26 lt1103/LT1105 applicatio n s i n for m atio n wu u u forward converter to define the switch voltage when s1 is off. this reset winding limits the maximum duty cycle allowed for the switch. this topology trades off reduced transformer size for increased complexity and parts count. a separate isolated feedback path is required for full isolation from input to output because voltages on the primary are no longer related to the dc output voltage during switch off time. the isolated feedback path can take several forms. a second transformer in a modulator/demodulator scheme provides the isolation, but with significant complexity. an optoisolator can be substituted for the transformer with a savings in volume to be traded off with component variations and possible aging problems with the optoisolator transfer function. finally, an extra winding closely coupled to the output inductor l1 can sense the flux in this element and give a representation of the output voltage when s1 is off. v out in continuous mode is defined as: v out = v in ? n ? dc the secondary voltage charges up l1 through d1 when s1 is on. when s1 is off, energy in l1 is transferred through free-wheeling diode d2 to c1. the extra transformer winding and diode d3 are needed in a single switch d1 v out c1 1:n lt1103 ai02 v in s1 d2 d3 l1 common simplified forward converter typical applicatio n s u 15v v sw LT1105 lt1103 ta04 i lim LT1105 fet connection lt1103 fet connection 15v v sw lt1103 lt1103 ta03
27 lt1103/LT1105 typical applicatio n s u osc c osc lt1103/LT1105 lt1103 ta05 choose 20khz f osc 200khz c osc = = = sf f osc i dc @ 0.66 t 66% 2.5v f osc 100 m a () () d v f osc () () ovlo r2 LT1105 lt1103 ta09 r1 ovlo th () choose ovlo th let r1 = 5k r2 = ? r1 ovlo th 2.5v setting oscillator frequency setting overvoltage lockout increasing oscillator maximum duty cycle decreasing oscillator maximum duty cycle synchronizing oscillator frequency to an external clock osc c osc lt1103/LT1105 lt1103 ta06 r i1 choose 0.66 dc 1.0 solve for x t x = 0 x 1.5 t i1 = x ?i = x ?100 m a t r = c osc = ? 1 ? (9dc ?6) 2 3.25v i1 2.5v f osc 100 m a () () 3x + 2x 2 () 9 osc c osc LT1105 lt1103 ta07 r i1 5v choose 0 dc 0.66 solve for x t x = 0 x 3 t i1 = x ?i = x ?100 m a t r = c osc = ? 1 + (6 ?9dc) 2 1.75v i1 2.5v f osc 100 m a () () 3x ?2x 2 () 9 osc c osc lt1103/LT1105 lt1103 ta08 1 m f 500ns isolation boundary 5v 0v 1:0.5
28 lt1103/LT1105 typical applicatio n s u lt1103 ground connections switch current path keep resistance low to bias winding output gnd lt1103 ta11a v sw fb v c gnd v in 15v osc to bias winding output gnd separate ground path switch current path keep resistance low lt1103 ta11b v sw fb v c gnd v in 15v osc to bias winding output high current ground path lt1103 ta12a gnd v sw i lim v in fb v c LT1105 ground connections
29 lt1103/LT1105 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n8 1197 0.100 0.010 (2.540 0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm)
30 lt1103/LT1105 n package 14-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n14 1197 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.045 ?0.065 (1.143 ?1.651) 0.065 (1.651) typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.005 (0.125) min 0.255 0.015* (6.477 0.381) 0.770* (19.558) max 3 1 2 4 5 6 7 8 9 10 11 12 13 14 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) package descriptio n u dimensions in inches (millimeters) unless otherwise noted.
31 lt1103/LT1105 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio n u dimensions in inches (millimeters) unless otherwise noted. t7 package 7-lead plastic to-220 (standard) (ltc dwg # 05-08-1422) 0.040 ?0.060 (1.016 ?1.524) 0.026 ?0.036 (0.660 ?0.914) t7 (to-220) (formed) 1197 0.135 ?0.165 (3.429 ?4.191) 0.700 ?0.728 (17.780 ?18.491) 0.045 ?0.055 (1.143 ?1.397) 0.165 ?0.180 (4.191 ?4.572) 0.095 ?0.115 (2.413 ?2.921) 0.013 ?0.023 (0.330 ?0.584) 0.620 (15.75) typ 0.155 ?0.195 (3.937 ?4.953) 0.152 ?0.202 (3.860 ?5.130) 0.260 ?0.320 (6.604 ?8.128) 0.147 ?0.155 (3.734 ?3.937) dia 0.390 ?0.415 (9.906 ?10.541) 0.330 ?0.370 (8.382 ?9.398) 0.460 ?0.500 (11.684 ?12.700) 0.570 ?0.620 (14.478 ?15.748) 0.230 ?0.270 (5.842 ?6.858)
32 lt1103/LT1105 ? linear technology corporation 1992 11035fd lt/tp 0998 rev d 2k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com related parts part number description comments lt1241 high speed current mode pulse width modulators up to 500khz operation lt1246 off-line current mode pwm 1mhz operation lt1248 power factor controller programmable frequency, 16-pin so lt1249 power factor controller 100khz, so-8 lt1508 power factor and pwm controller voltage mode lt1509 power factor and pwm controller current mode minimum parts count fully-isolated flyback 100khz 50w converter typical applicatio n u 220k 1w 330 w 0.1 m f 499 w 39 m f 25v 1000pf 100 w 1n4148 16.2k 1% 5.36k 1% buk426-800a mbr2045 10 m h 5v 10a 50v 470 m f 35v 3600 m f windings for optional 12v dc outputs 10 w 1 m f 25v 220 m f 385v bav21 bav21 390pf 1.5ke300a 5w mur150 bridge rectifier + line filter 85v ac to 270v ac + transformer data: coiltronics - ctx110228-3 l (pri) = 1.6mh n pri :n sec = 1:0.05 n bias :n sec = 1:0.27 0.047 m f lt1103 ta01 *output capacitor is three 1200 m f, 50v capacitors in parallel to achieve required ripple current rating and low esr. optional output filter v in v sw v c fb gnd osc 15v lt1103 danger!! high voltage!! + + + + + danger!! lethal voltages present C see text load regulation i out (a) 0 v out (v) 5.05 5.15 5.25 8 lt1103 ta14 4.95 4.85 4.75 2 4 6 10 4.80 4.90 5.00 5.10 5.20 1 3 579 85v ac 110v ac 270v ac 220v ac

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